Multiplicative square root algorithms for FPGAs

Florent De Dinechin 1, 2 Mioara Maria Joldes 1, 2 Bogdan Pasca 2, 1 Guillaume Revy 1, 2
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Most current square root implementations for FPGAs use a digit recurrence algorithm which is well suited to their LUT structure. However, recent computing-oriented FPGAs include embedded multipliers and RAM blocks which can also be used to implement quadratic convergence algorithms, very high radix digit recurrences, or polynomial approximation algorithms. The cost of these solutions is evaluated and compared, and a complete implementation of a polynomial approach is presented within the open-source FloPoCo framework. It allows a much shorter latency and a higher frequency than the classical approach. The cost of IEEE-compliant correct rounding using such approximation algorithms is shown to be very high, and faithful (last-bit accurate) operators are advocated in this case.
Mots-clés : Square-root FPGA
Type de document :
Communication dans un congrès
International Conference on Field Programmable Logic and Applications, Aug 2010, Milano, Italy. IEEE, pp.14, 2010, 〈10.1109/FPL.2010.112〉
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Florent De Dinechin, Mioara Maria Joldes, Bogdan Pasca, Guillaume Revy. Multiplicative square root algorithms for FPGAs. International Conference on Field Programmable Logic and Applications, Aug 2010, Milano, Italy. IEEE, pp.14, 2010, 〈10.1109/FPL.2010.112〉. 〈ensl-00475779v2〉

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