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Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors

Qingda Lu 1 Christophe Alias 2 Uday Bondhugula 3 Thomas Henretty 1 Sriram Krishnamoorthy 4 J. Ramanujam 5 Atanas Rountev 1 P. Sadayappan 6 Yongjian Chen 7 Haibo Lin 8
1 OSU - Ohio State University [Columbus]
2 COMPSYS - Compilation and embedded computing systems
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
3 CSA - Department of Computer Science and Automation [Bangalore]
4 PNNL - Pacific Northwest National Laboratory
5 ECE - Department of Electrical and Computer Engineering - Louisiana State University
6 CSE - Department of Computer Science and Engineering [Columbus]
7 Intel Corp.
8 Department of Vehicle and Traffic
Abstract : With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bank-interleaved distribution of the address space. Although such an organization is effective for avoiding access hot-spots, it can cause a significant number of non-local L2 accesses for many commonly occurring regular data access patterns. In this paper we develop a compile-time framework for data locality optimization via data layout transformation. Using a polyhedral model, the program's localizability is determined by analysis of its index set and array reference functions, followed by non-canonical data layout transformation to reduce non-local accesses for localizable computations. Simulation-based results on a 16-core 2D tiled CMP demonstrate the effectiveness of the approach. The developed program transformation technique is also useful in several other data layout transformation contexts.
Keywords : Data Layout Optimization Polyhedral Model NUCA Cache
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  • HAL Id : ensl-01664020, version 1

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Qingda Lu, Christophe Alias, Uday Bondhugula, Thomas Henretty, Sriram Krishnamoorthy, et al.. Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors. IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT'09), Sep 2009, Raleigh, United States. ⟨ensl-01664020⟩

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