34 Gb/s PDM-QPSK coherent receiver using SiGe ADCs and a single FPGA for digital signal processing

Eric Dutisseuil 1 Jean-Marc Tanguy 1 Adrian Voicila 1 Rémi Laube 2 Francois Bore 2 Honore Takeugming 3, 4 Florent de Dinechin 3, 4, 5 Frédéric Cérou 6 And Gabriel Charlet 1
1 Alcatel-Lucent Bell Labs France [Nozay]
2 E2V - E2V Semiconductors SAS [Saint-Egrève]
3 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
4 LIP - Laboratoire de l'Informatique du Parallélisme
5 ARIC - Arithmetic and Computing
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
6 ASPI - Applications of interacting particle systems to statistics
IRMAR - Institut de Recherche Mathématique de Rennes, Inria Rennes – Bretagne Atlantique
Abstract : A fully reprogrammable coherent receiver using an integrated coherent front end, four high speed ADCs and powerful FPGAs is reported and tested against optical noise level, chromatic dispersion and PMD for various equalizer filter length.
Document type :
Conference papers
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https://hal-ens-lyon.archives-ouvertes.fr/ensl-00766801
Contributor : Florent de Dinechin <>
Submitted on : Wednesday, December 19, 2012 - 9:45:21 AM
Last modification on : Wednesday, November 20, 2019 - 3:13:09 AM

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  • HAL Id : ensl-00766801, version 1

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Citation

Eric Dutisseuil, Jean-Marc Tanguy, Adrian Voicila, Rémi Laube, Francois Bore, et al.. 34 Gb/s PDM-QPSK coherent receiver using SiGe ADCs and a single FPGA for digital signal processing. Optical Fiber Communication Conference, Mar 2012, nc, United States. pp.OM3H.7. ⟨ensl-00766801⟩

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