Arithmetic core generation using bit heaps

Nicolas Brunie 1, 2, 3 Florent De Dinechin 1, 2, 4 Matei Istoan 1, 4 Guillaume Sergent 1 Kinga Illyes 5 Bogdan Popa 5
2 ARIC - Arithmetic and Computing
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
4 SOCRATE - Software and Cognitive radio for telecommunications
Inria Grenoble - Rhône-Alpes, UCBL - Université Claude Bernard Lyon 1, CITI - CITI Centre of Innovation in Telecommunications and Integration of services
Abstract : A bit heap is a data structure that holds the unevaluated sum of an arbitrary number of bits, each weighted by some power of two. Most advanced arithmetic cores can be viewed as involving one or several bit heaps. We claim here that this point of view leads to better global optimization at the algebraic level, at the circuit level, and in terms of software engineering. To demonstrate it, a generic software framework is introduced for the definition and optimization of bit heaps. This framework, targeting DSP-enabled FPGAs, is developed within the open-source FloPoCo arithmetic core generator. Its versatility is demonstrated on several examples: multipliers, complex multipliers, polynomials, and discrete cosine transform.
Type de document :
Communication dans un congrès
23rd International Conference on Field Programmable Logic and Applications, Sep 2013, Porto, Portugal. pp.1-8, 2013
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Contributeur : Florent De Dinechin <>
Soumis le : vendredi 29 novembre 2013 - 16:06:43
Dernière modification le : jeudi 8 février 2018 - 11:10:03
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Nicolas Brunie, Florent De Dinechin, Matei Istoan, Guillaume Sergent, Kinga Illyes, et al.. Arithmetic core generation using bit heaps. 23rd International Conference on Field Programmable Logic and Applications, Sep 2013, Porto, Portugal. pp.1-8, 2013. 〈ensl-00738412v2〉

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