Floating-Point Exponentiation Units for Reconfigurable Computing - Archive ouverte HAL Access content directly
Journal Articles ACM Transactions on Reconfigurable Technology and Systems (TRETS) Year : 2013

Floating-Point Exponentiation Units for Reconfigurable Computing

(1, 2) , (3) , (3) , (1)
1
2
3

Abstract

The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function $x^y$ as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.
Fichier principal
Vignette du fichier
2012-TRETS-Exponentiation.pdf (392.74 Ko) Télécharger le fichier
Origin : Publisher files allowed on an open archive
Loading...

Dates and versions

ensl-00718637 , version 1 (17-07-2012)

Identifiers

Cite

Florent de Dinechin, Pedro Echeverria, Marisa Lopez-Vallejo, Bogdan Pasca. Floating-Point Exponentiation Units for Reconfigurable Computing. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2013, 6 (1), pp.4:1--4:15. ⟨10.1145/2457443.2457447⟩. ⟨ensl-00718637⟩
208 View
749 Download

Altmetric

Share

Gmail Facebook Twitter LinkedIn More