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Floating-Point Exponentiation Units for Reconfigurable Computing

Abstract : The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function $x^y$ as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.
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Submitted on : Tuesday, July 17, 2012 - 5:11:58 PM
Last modification on : Monday, May 16, 2022 - 4:58:02 PM
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Florent de Dinechin, Pedro Echeverria, Marisa Lopez-Vallejo, Bogdan Pasca. Floating-Point Exponentiation Units for Reconfigurable Computing. ACM Transactions on Reconfigurable Technology and Systems (TRETS), ACM, 2013, 6 (1), pp.4:1--4:15. ⟨10.1145/2457443.2457447⟩. ⟨ensl-00718637⟩



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