Simultaneous Branch and Warp Interweaving for Sustained GPU Performance

Abstract : Single-Instruction Multiple-Thread (SIMT) micro-architectures implemented in Graphics Processing Units (GPUs) run fine-grained threads in lockstep by grouping them into units, referred to as warps, to amortize the cost of instruction fetch, decode and control logic over multiple execution units. As individual threads take divergent execution paths, their processing takes place sequentially, defeating part of the efficiency advantage of SIMD execution. We present two complementary techniques that mitigate the impact of thread divergence on SIMT micro-architectures. Both techniques relax the SIMD execution model by allowing two distinct instructions to be scheduled to disjoint subsets of the the same row of execution units, instead of one single instruction. They increase flexibility by providing more thread grouping opportunities than SIMD, while preserving the affinity between threads to avoid introducing extra memory divergence. We consider (1) co-issuing instructions from different divergent paths of the same warp and (2) co-issuing instructions from different warps. To support (1), we introduce a novel thread reconvergence technique that ensures threads are run back in lockstep at control-flow reconvergence points without hindering their ability to run branches in parallel. We propose a lane shuffling technique to allow solution (2) to benefit from inter-warp correlations in divergence patterns. The combination of all these techniques improves performance by 23% on a set of regular GPGPU applications and by 40% on irregular applications, while maintaining the same instruction-fetch and processing-unit resource requirements as the contemporary Fermi GPU architecture.
Document type :
Conference papers
Complete list of metadatas

Cited literature [29 references]  Display  Hide  Download

https://hal-ens-lyon.archives-ouvertes.fr/ensl-00649650
Contributor : Caroline Collange <>
Submitted on : Wednesday, May 2, 2012 - 8:58:39 PM
Last modification on : Friday, September 20, 2019 - 4:36:07 PM
Long-term archiving on : Thursday, December 15, 2016 - 3:56:07 AM

File

sbiswi.pdf
Files produced by the author(s)

Identifiers

Collections

Citation

Nicolas Brunie, Sylvain Collange, Gregory Diamos. Simultaneous Branch and Warp Interweaving for Sustained GPU Performance. 39th Annual International Symposium on Computer Architecture (ISCA), Portland, OR, United States. pp.49 - 60, ⟨10.1109/ISCA.2012.6237005⟩. ⟨ensl-00649650v2⟩

Share

Metrics

Record views

1199

Files downloads

829