Affine Vector Cache for memory bandwidth savings

Sylvain Collange 1, 2, * Alexandre Kouyoumdjian 1, 2
* Auteur correspondant
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Preserving memory locality is a major issue in highly-multithreaded architectures such as GPUs. These architectures hide latency by maintaining a large number of threads in flight. As each thread needs to maintain a private working set, all threads collectively put tremendous pressure on on-chip memory arrays, at significant cost in area and power. We show that thread-private data in GPU-like implicit SIMD architectures can be compressed by a factor up to 16 by taking advantage of correlations between values held by different threads. We propose the Affine Vector Cache, a compressed cache design that complements the first level cache. Evaluation by simulation on the SDK and Rodinia benchmarks shows that a 32KB L1 cache assisted by a 16KB AVC presents a 59% larger usable capacity on average compared to a single 48KB L1 cache. It results in a global performance increase of 5.7% along with an energy reduction of 11% for a negligible hardware cost.
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Rapport
2011
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https://hal-ens-lyon.archives-ouvertes.fr/ensl-00649200
Contributeur : Sylvain Collange <>
Soumis le : mercredi 7 décembre 2011 - 12:16:44
Dernière modification le : mardi 16 janvier 2018 - 15:42:37
Document(s) archivé(s) le : vendredi 16 novembre 2012 - 14:40:37

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Sylvain Collange, Alexandre Kouyoumdjian. Affine Vector Cache for memory bandwidth savings. 2011. 〈ensl-00649200〉

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