N. E. Abel, P. P. Budnik, D. J. Kuck, Y. Muraoka, R. S. Northcote et al., QUIL : a language for an array processing computer ?, Proceedings of the spring joint computer conference, AFIPS '69 (Spring), pp.57-73, 1969.

C. S. Boyer, M. Meng, J. Tarjan, D. Sheaffer, J. W. Lee et al., A benchmark suite for heterogeneous computing ?, IEEE Workload Characterization Symposium, vol.0, pp.44-54, 2009.

S. Collange, Analyse de l'architecture GPU Tesla, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00443875

S. Collange, M. Daumas, D. Defour, and D. Parello, Etude comparée et simulation d'algorithmes de branchements pour le GPGPU ?, SYMPosium en Architectures nouvelles de machines (SYMPA), 2009.

S. Collange, D. Defour, and A. Tisserand, Power Consumption of GPUs from a Software Perspective, ICCS Lecture Notes in Computer Science, vol.5544, pp.922-931, 2009.
DOI : 10.1007/978-3-642-01970-8_92
URL : https://hal.archives-ouvertes.fr/hal-00348672

S. Collange, D. Defour, and Y. Zhang, Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations, Europar 3rd Workshop on Highly Parallel Processing on a Chip (HPPC), pp.46-55, 2009.
DOI : 10.1007/978-3-642-14122-5_8
URL : https://hal.archives-ouvertes.fr/hal-00396719

J. D. Collins, D. M. Tullsen, and H. Wang, Control Flow Optimization Via Dynamic Reconvergence Prediction, 37th International Symposium on Microarchitecture (MICRO-37'04), pp.129-140, 2004.
DOI : 10.1109/MICRO.2004.13
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.59.6434

B. W. Coon and J. E. Lindholm, ? System and method for managing divergent threads in a SIMD architecture ?, US Patent 7353369, 2008.

B. W. Coon, J. R. Nickolls, J. E. Lindholm, and S. D. Tzvetkov, ? Structured programming control flow in a SIMD architecture ?, 2011.

E. Demers, ? Evolution of AMD's Graphics Core, and Preview of Graphics Core Next ?, AMD Fusion Developer Summit keynote, 2011.

W. Fung and T. Aamodt, Thread block compaction for efficient SIMT control flow, 2011 IEEE 17th International Symposium on High Performance Computer Architecture, pp.25-36, 2011.
DOI : 10.1109/HPCA.2011.5749714

W. W. Fung, I. Sham, G. Yuan, and T. M. Aamodt, Dynamic warp formation, ACM Transactions on Architecture and Code Optimization, vol.6, issue.2, pp.1-737, 2009.
DOI : 10.1145/1543753.1543756

M. Gebhart, D. R. Johnson, D. Tarjan, S. W. Keckler, W. J. Dally et al., ? Energy-efficient mechanisms for managing thread context in throughput processors, Proceeding of the 38th annual international symposium on Computer architecture, pp.235-246, 2011.

. Int, Intel G45 Express Chipset Graphics Controller PRM, Volume Four : Subsystem and Cores, 2009.

R. Keryell, N. Paris, and . Counter, New Optimization for the dynamic scheduling of SIMD Control Flow ?, Proceedings of the 1993 International Conference on Parallel Processing, pp.93-184, 1993.

D. H. Lawrie, T. Layman, D. Baer, and J. M. Randal, Glypnir---a programming language for Illiac IV, Communications of the ACM, vol.18, issue.3, pp.157-164, 1975.
DOI : 10.1145/360680.360687

A. Levinthal and T. Porter, Chap -a SIMD graphics processor ?, Proceedings of the 11th annual conference on Computer graphics and interactive techniques, SIGGRAPH '84, pp.77-82, 1984.

J. Meng, D. Tarjan, and K. Skadron, ? Dynamic warp subdivision for integrated branch and memory divergence tolerance ?, SIGARCH Comput, Archit. News, vol.38, pp.3-3, 2010.
DOI : 10.1145/1815961.1815992

Y. Takahashi, Mechanism for SIMD Execution of SPMD Programs ?, Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97, HPC- ASIA '97, pp.529-534, 1997.

F. Zhang, H. D. Hollander, and E. , Using hammock graphs to structure programs, IEEE Transactions on Software Engineering, vol.30, issue.4, pp.231-245, 2004.
DOI : 10.1109/TSE.2004.1274043