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Assouplir les contraintes des architectures SIMT à faible coût

Nicolas Brunie 1, 2, 3, * Sylvain Collange 1, 2, *
* Corresponding author
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Parallel architectures following the SIMT model such as GPUs benefit from application regularity by issuing concurrent threads running in lockstep on SIMD units. As threads take different paths across the control-flow graph, lockstep execution is partially lost, and must be regained whenever possible in order to maximize the occupancy of SIMD units. In this paper, we propose two techniques to handle SIMT control divergence and identify reconvergence points. The most advanced one operates in constant space and handles indirect jumps and recursion. We evaluate a hardware implementation which leverage the existing memory divergence management unit. In terms of performance, this solution is at least as efficient as state of the art techniques in use in current GPUs.
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Contributor : Caroline Collange <>
Submitted on : Wednesday, December 7, 2011 - 11:53:09 AM
Last modification on : Friday, June 25, 2021 - 3:40:03 PM
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  • HAL Id : ensl-00649186, version 1



Nicolas Brunie, Sylvain Collange. Assouplir les contraintes des architectures SIMT à faible coût. 2011. ⟨ensl-00649186⟩



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