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How to Square Floats Accurately and Efficiently on the ST231 Integer Processor

Claude-Pierre Jeannerod 1, 2, * Jingyan Jourdan-Lu 1, 2, 3 Christophe Monat 4 Guillaume Revy 5
* Corresponding author
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
2 LIP - Laboratoire de l'Informatique du Parallélisme
3 ARENAIRE - Arithmétique des ordinateurs
ST-GRENOBLE - STMicroelectronics [Grenoble]
4 ST-GRENOBLE - STMicroelectronics [Grenoble]
5 DALI - Digits, Architectures et Logiciels Informatiques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, UPVD - Université de Perpignan Via Domitia
Abstract : We consider the problem of computing IEEE floating-point squares by means of integer arithmetic. We show how to exploit the specific properties of squaring in order to design and implement algorithms that have much lower latency than those for general multiplication, while still guaranteeing correct rounding. Our algorithms are parameterized by the floating-point format, aim at high instruction-level parallelism (ILP) exposure, and cover all rounding modes. We show further that their C implementation for the binary32 format yields efficient codes for targets like the ST231 VLIW integer processor from ST Microelectronics, with a latency at least 1.75x smaller than that of general multiplication in the same context.
Keywords : VLIW integer processor squaring binary floating-point arithmetic correct rounding IEEE 754 instruction level parallelism C software implementation
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https://hal-ens-lyon.archives-ouvertes.fr/ensl-00644147
Contributor : Claude-Pierre Jeannerod <>
Submitted on : Wednesday, November 23, 2011 - 4:41:51 PM
Last modification on : Thursday, November 21, 2019 - 2:26:47 AM

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ENS-LYON | CNRS | INRIA | LIP | UNIV-PERP | DALI | LIRMM | MIPS | UNIV-MONTPELLIER | UNIV-LYON1 | UDL

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Claude-Pierre Jeannerod, Jingyan Jourdan-Lu, Christophe Monat, Guillaume Revy. How to Square Floats Accurately and Efficiently on the ST231 Integer Processor. ARITH: Computer Arithmetic, Jul 2011, Tübingen, Germany. pp.77-81, ⟨10.1109/ARITH.2011.19⟩. ⟨ensl-00644147⟩

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