Numerical stability in mathematical analysis, Proceedings of the 1968 IFIP Congress, pp.11-23, 1969. ,
The POWER7 Binary Floating-Point Unit, 2011 IEEE 20th Symposium on Computer Arithmetic, 2011. ,
DOI : 10.1109/ARITH.2011.21
Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition, 17th IEEE Symposium on Computer Arithmetic (ARITH'05), pp.42-51, 2005. ,
DOI : 10.1109/ARITH.2005.22
Designing custom arithmetic data paths with FloPoCo, IEEE Design & Test of Computers, 2011. ,
Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy, IEEE Computer Architecture Letters, vol.6, issue.1, pp.13-16, 2007. ,
DOI : 10.1109/L-CA.2007.1
MPFR, ACM Transactions on Mathematical Software, vol.33, issue.2, pp.1-13, 2007. ,
DOI : 10.1145/1236463.1236468
URL : https://hal.archives-ouvertes.fr/inria-00070266
Fused multiply add split for multiple precision arithmetic, 2005. ,
A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design, 18th IEEE Symposium on Computer Arithmetic (ARITH '07), pp.69-76, 2007. ,
DOI : 10.1109/ARITH.2007.5
Advanced Arithmetic for the Digital Computer: Design of Arithmetic Units, 2002. ,
Floating-point fused multiply-add with reduced latency, Proceedings of the 2002 IEEE International Conference on Computer Design : VLSI in Computers and Processors, 2002. ,
Fused multiply-add microarchitecture comprising separate early-normalizing multiply and add pipelines, IEEE Symposium on Computer Arithmetic, pp.123-128, 2011. ,
Overcoming double-rounding errors under IEEE 754-2008 using software, Asilomar Conference on Signals, Systems, and Computers, pp.1399-1401, 2010. ,
Method and system for multi-precision computation. US Patent, 2011. ,
Handbook of Floating-Point Arithmetic, Nathalie Revol, 2009. ,
DOI : 10.1007/978-0-8176-4705-6
URL : https://hal.archives-ouvertes.fr/ensl-00379167
Rundungsfehleranalyse einiger Verfahren zur Summation endlicher Summen, ZAMM - Zeitschrift f??r Angewandte Mathematik und Mechanik, vol.50, issue.1, pp.39-51, 1974. ,
DOI : 10.1002/zamm.19740540106
Correction d'une somme en arithmetique a virgule flottante, Numerische Mathematik, vol.19, issue.5 ,
DOI : 10.1007/BF01404922
Algorithms for arbitrary precision floating point arithmetic, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic, pp.132-144, 1991. ,
DOI : 10.1109/ARITH.1991.145549
Three-path fused multiply-adder circuit. US Patent, 2008. ,
Register organization for media processing, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550), pp.375-386, 2000. ,
DOI : 10.1109/HPCA.2000.824366
Accurate Floating-Point Summation Part I: Faithful Rounding, SIAM Journal on Scientific Computing, vol.31, issue.1, pp.189-224, 2008. ,
DOI : 10.1137/050645671
Multiple path ieee floating-point fused multiplyadd, 46th Midwset Symposium on Circuits and Systems, 2003. ,