Skip to Main content Skip to Navigation
Conference papers

An FPGA architecture for solving the Table Maker's Dilemma

Florent de Dinechin 1, 2 Jean-Michel Muller 1 Bogdan Pasca 1 Alexandru Plesco 3
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
2 LIP - Laboratoire de l'Informatique du Parallélisme
3 COMPSYS - Compilation and embedded computing systems
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Solving the Table Maker's Dilemma, for a given function and a given target floating-point format, requires testing the value of the function, with high precision, at a very large number of consecutive values. We give an algorithm that allows for performing such computations on a very regular architecture, and present an FPGA implementation of that algorithm.
Keywords : table maker's dilemma floating-point arithmetic correct rounding elementary functions FPGA
Document type :
Conference papers
Complete list of metadata

Cited literature [8 references]  Display  Hide  Download
https://hal-ens-lyon.archives-ouvertes.fr/ensl-00640063
Contributor : Jean-Michel Muller <>
Submitted on : Monday, November 14, 2011 - 1:49:41 PM
Last modification on : Friday, June 25, 2021 - 3:40:03 PM
Long-term archiving on: : Wednesday, February 15, 2012 - 2:20:41 AM

File

Vignette du document
PID1914885.pdf
Files produced by the author(s)

Identifiers

Collections

CNRS | INRIA | LIP | ENS-LYON | UNIV-LYON1 | UDL

Citation

Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, Alexandru Plesco. An FPGA architecture for solving the Table Maker's Dilemma. Application-Specific Systems, Architectures and Processors (ASAP), 2011 IEEE International Conference on, Sep 2011, Santa Monica, United States. pp.187-194, ⟨10.1109/ASAP.2011.6043267⟩. ⟨ensl-00640063⟩

Export

BibTeX TEI DC DCterms EndNote

Share

Metrics

Record views

775

Files downloads

498