An FPGA architecture for solving the Table Maker's Dilemma

Florent de Dinechin (1, 2) , Jean-Michel Muller (1) , Bogdan Pasca (1) , Alexandru Plesco (3)

1 ARENAIRE - Computer arithmetic
2 LIP - Laboratoire de l'Informatique du Parallélisme
3 COMPSYS - Compilation and embedded computing systems

Solving the Table Maker's Dilemma, for a given function and a given target floating-point format, requires testing the value of the function, with high precision, at a very large number of consecutive values. We give an algorithm that allows for performing such computations on a very regular architecture, and present an FPGA implementation of that algorithm.

Keywords: table maker's dilemma; floating-point arithmetic; correct rounding; elementary functions; FPGA

Domains: Computer Science [cs]; Other [cs.OH]

Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, Alexandru Plesco. An FPGA architecture for solving the Table Maker's Dilemma. Application-Specific Systems, Architectures and Processors (ASAP), 2011 IEEE International Conference on, Sep 2011, Santa Monica, United States. pp.187-194, ⟨10.1109/ASAP.2011.6043267⟩. ⟨ensl-00640063⟩