An FPGA architecture for solving the Table Maker's Dilemma

Florent de Dinechin; Jean-Michel Muller; Bogdan Pasca; Alexandru Plesco

An FPGA architecture for solving the Table Maker's Dilemma

Florent de Dinechin ^{1, 2} Jean-Michel Muller ¹ Bogdan Pasca ¹ Alexandru Plesco ³

1 ARENAIRE - Computer arithmetic

Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme

2 LIP - Laboratoire de l'Informatique du Parallélisme

3 COMPSYS - Compilation and embedded computing systems

Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme

Abstract : Solving the Table Maker's Dilemma, for a given function and a given target floating-point format, requires testing the value of the function, with high precision, at a very large number of consecutive values. We give an algorithm that allows for performing such computations on a very regular architecture, and present an FPGA implementation of that algorithm.

Keywords : table maker's dilemma floating-point arithmetic correct rounding elementary functions FPGA

Document type :

Conference papers

Domain :

Computer Science [cs] / Other [cs.OH]

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https://hal-ens-lyon.archives-ouvertes.fr/ensl-00640063
Contributor : Jean-Michel Muller <>
Submitted on : Monday, November 14, 2011 - 1:49:41 PM
Last modification on : Thursday, February 7, 2019 - 4:53:10 PM
Long-term archiving on : Wednesday, February 15, 2012 - 2:20:41 AM

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An FPGA architecture for solving the Table Maker's Dilemma

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