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Journal Articles IEEE Transactions on Circuits and Systems Part 2 Analog and Digital Signal Processing Year : 2012

Multiplication by rational constants

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Abstract

Multiplications by simple rational constants often appear in fixed-point or floating-point application code, for instance in the form of division by an integer constant. The hardware implementation of such operations is of practical interest to FPGA-accelerated computing. It is well known that the binary representation of rational constants is eventually periodic. This article shows how this feature can be exploited to implement multiplication by a rational constant in a number of additions that is logarithmic in the precision. An open-source implementation of these techniques is provided, and is shown to be practically relevant for constants with small numerators and denominators, where it provides improvements of 20 to 40\% in area with respect to the state of the art. It is also shown that for such constants, the additional cost for a correctly rounded result is very small, and that correct rounding very often comes for free in practice.
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Dates and versions

ensl-00610328 , version 1 (21-07-2011)
ensl-00610328 , version 2 (04-11-2011)
ensl-00610328 , version 3 (15-11-2011)

Identifiers

Cite

Florent de Dinechin. Multiplication by rational constants: LIP research report 2011-3. IEEE Transactions on Circuits and Systems Part 2 Analog and Digital Signal Processing, 2012, pp.00. ⟨10.1109/TCSII.2011.2177706⟩. ⟨ensl-00610328v3⟩
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