Skip to Main content Skip to Navigation
Journal articles

Improved Design of High-Performance Parallel Decimal Multipliers

Alvaro Vazquez 1, * Elisardo Antelo 2 Paolo Montuschi 3 
* Corresponding author
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : The new generation of high-performance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multipliers. In this paper, we describe the architectures of two parallel decimal multipliers. The parallel generation of partial products is performed using signed-digit radix-10 or radix-5 recodings of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a decimal multioperand carry-save addition algorithm that uses unconventional (non BCD) decimal-coded number systems. We further detail these techniques and present the new improvements to reduce the latency of the previous designs, which include: optimized digit recoders for the generation of 2^n-tuples (and 5-tuples), decimal carry-save adders (CSAs) combining different decimal-coded operands, and carry-free adders implemented by special designed bit counters. Moreover, we detail a design methodology that combines all these techniques to obtain efficient reduction trees with different area and delay trade-offs for any number of partial products generated. Evaluation results for 16-digit operands show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix--8 parallel binary multipliers and outperform the figures of previous alternatives for decimal multiplication.
Document type :
Journal articles
Complete list of metadata
Contributor : Alvaro Vazquez Connect in order to contact the contributor
Submitted on : Thursday, January 27, 2011 - 6:08:52 PM
Last modification on : Friday, February 4, 2022 - 3:31:41 AM


  • HAL Id : ensl-00560255, version 1



Alvaro Vazquez, Elisardo Antelo, Paolo Montuschi. Improved Design of High-Performance Parallel Decimal Multipliers. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2010, 59 (5), pp.679-693. ⟨ensl-00560255⟩



Record views