Computing floating-point square roots via bivariate polynomial evaluation

Claude-Pierre Jeannerod 1, 2, * Hervé Knochel 3 Christophe Monat 3 Guillaume Revy 4
* Corresponding author
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
4 DALI - Digits, Architectures et Logiciels Informatiques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, UPVD - Université de Perpignan Via Domitia
Abstract : In this paper we show how to reduce the computation of correctly-rounded square roots of binary floating-point data to the fixed-point evaluation of some particular integer polynomials in two variables. By designing parallel and accurate evaluation schemes for such bivariate polynomials, we show further that this approach allows for high instruction-level parallelism (ILP) exposure, and thus potentially low latency implementations. Then, as an illustration, we detail a C implementation of our method in the case of IEEE 754-2008 binary32 floating-point data (formerly called single precision in the 1985 version of the IEEE 754 standard). This software implementation, which assumes 32-bit integer arithmetic only, is almost complete in the sense that it supports special operands, subnormal numbers, and all rounding modes, but not exception handling (that is, status flags are not set). Finally we have carried out experiments with this implementation using the ST200 VLIW compiler from STMicroelectronics. The results obtained demonstrate the practical interest of our approach in that context: for all rounding modes, the generated assembly code is optimally scheduled and has indeed low latency (23 cycles).
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Contributor : Claude-Pierre Jeannerod <>
Submitted on : Tuesday, January 25, 2011 - 11:06:38 AM
Last modification on : Thursday, February 7, 2019 - 2:25:00 PM

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Claude-Pierre Jeannerod, Hervé Knochel, Christophe Monat, Guillaume Revy. Computing floating-point square roots via bivariate polynomial evaluation. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2011, 60 (2), pp.214-227. ⟨10.1109/TC.2010.152⟩. ⟨ensl-00559236⟩



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