C. Alias, F. Baray, and A. Darte, Bee+cl@k: An implementation of lattice-based memory reuse in the source-to-source translator ROSE, International ACM Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), 2007.

C. Bastoul, A. Cohen, S. Girbal, S. Sharma, and O. Temam, Putting Polyhedral Loop Transformations to Work, 2003.
DOI : 10.1007/978-3-540-24644-2_14

URL : https://hal.archives-ouvertes.fr/inria-00071681

U. Bondhugula, A. Hartono, J. Ramanujam, and P. Sadayappan, A practical automatic polyhedral parallelizer and locality optimizer, ACM International Conference on Programming Languages Design and Implementation (PLDI'08, pp.101-113, 2008.

P. Boulet, P. Feautrier, and P. Clauss, Scanning polyhedra without Do-loops Counting solutions to linear and nonlinear constraints through Ehrhart polynomials: Applications to analyze and transform scientific programs, IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT'98 International Conference on Supercomputing (ICS'96, pp.4-9, 1996.

F. De-dinechin, A flexible floating-point logarithm for reconfigurable computers Lip research report rr2010-22, 2010.

F. De-dinechin, M. Joldes, B. Pasca, and G. Revy, Multiplicative Square Root Algorithms for FPGAs, 2010 International Conference on Field Programmable Logic and Applications, 2010.
DOI : 10.1109/FPL.2010.112

URL : https://hal.archives-ouvertes.fr/ensl-00475779

F. De-dinechin, C. Klein, and B. Pasca, Generating high-performance custom floating-point pipelines, 2009 International Conference on Field Programmable Logic and Applications, 2009.
DOI : 10.1109/FPL.2009.5272553

URL : https://hal.archives-ouvertes.fr/ensl-00379154

F. De-dinechin and B. Pasca, Floating-point exponential functions for DSPenabled FPGAs, 2010.
URL : https://hal.archives-ouvertes.fr/ensl-00506125

F. De-dinechin, B. Pasca, . Cret¸, O. Cret¸, and R. Tudoran, An FPGA-specific approach to floating-point accumulation and sum-of-products, 2008 International Conference on Field-Programmable Technology, pp.33-40, 2008.
DOI : 10.1109/FPT.2008.4762363

URL : https://hal.archives-ouvertes.fr/ensl-00268348

P. Feautrier, Parametric integer programming, RAIRO - Operations Research, vol.22, issue.3, pp.243-268, 1988.
DOI : 10.1051/ro/1988220302431

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.30.9957

S. Gupta, N. Dutt, R. Gupta, and A. Nicolau, SPARK: a high-level synthesis framework for applying parallelizing compiler transformations, 16th International Conference on VLSI Design, 2003. Proceedings., pp.461-466, 2003.
DOI : 10.1109/ICVD.2003.1183177

A. W. Lim and M. S. Lam, Maximizing parallelism and minimizing synchronization with affine transforms, Proceedings of the 24th ACM SIGPLAN-SIGACT symposium on Principles of programming languages , POPL '97, 1997.
DOI : 10.1145/263699.263719

E. Martin, O. Sentieys, H. Dubois, and J. L. Philippe, GAUT: An architectural synthesis tool for dedicated signal processors, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference, pp.14-19, 1993.
DOI : 10.1109/EURDAC.1993.410610

A. Plesco, Program Transformations and Memory Architecture Optimizations for High-Level Synthesis of Hardware Accelerators, 2010.
URL : https://hal.archives-ouvertes.fr/tel-00544349

J. Xue, Loop Tiling for Parallelism, 2000.
DOI : 10.1007/978-1-4615-4337-4