Automatic Generation of FPGA-Specific Pipelined Accelerators

Christophe Alias 1, * Bogdan Pasca 2 Alexandru Plesco 1
* Corresponding author
1 COMPSYS - Compilation and embedded computing systems
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
2 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Recent increase in the complexity of the circuits has brought high-level synthesis tools as a must in the digital circuit design. However, these tools come with several limitations, and one of them is the efficient use of pipelined arithmetic operators. This paper explains how to generate efficient hardware with pipelined operators for regular codes with perfect loop nests. The part to be mapped to the operator is identified, then the program is scheduled so that each operator result is available exactly at the time it is needed by the operator, keeping the operator busy and avoiding the use of a temporary buffer. Finally, we show how to generate the VHDL code for the control unit and how to link it with specialized pipelined floating-point operators generated using open-source FloPoCo tool. The method has been implemented in the Bee research compiler and experimental results on DSP kernels show promising results with a minimum of 94% efficient utilization of the pipelined operators for a complex kernel.
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Submitted on : Wednesday, December 22, 2010 - 12:30:56 PM
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Christophe Alias, Bogdan Pasca, Alexandru Plesco. Automatic Generation of FPGA-Specific Pipelined Accelerators. International Symposium on Applied Reconfigurable Computing (ARC'11), Mar 2011, Belfast, United Kingdom. ⟨ensl-00549682⟩



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