Techniques and tools for implementing IEEE 754 floating-point arithmetic on VLIW integer processors

Abstract : Recently, some high-performance IEEE 754 single precision floating-point software has been designed, which aims at best exploiting some features (integer arithmetic, parallelism) of the STMicroelectronics ST200 Very Long Instruction Word (VLIW) processor. We review here the techniques and software tools used or developed for this design and its implementation, and how they allowed very high instruction-level parallelism (ILP) exposure. Those key points include a hierarchical description of function evaluation algorithms, the exploitation of the standard encoding of floating-point data, the automatic generation of fast and accurate polynomial evaluation schemes, and some compiler optimizations.
Type de document :
Communication dans un congrès
4th International Workshop on Parallel and Symbolic Computation (PASCO'10), Jul 2010, Grenoble, France. ACM, pp.1-9, 2010, 〈10.1145/1837210.1837212〉
Liste complète des métadonnées

https://hal-ens-lyon.archives-ouvertes.fr/ensl-00549467
Contributeur : Claude-Pierre Jeannerod <>
Soumis le : mercredi 22 décembre 2010 - 09:11:57
Dernière modification le : vendredi 20 juillet 2018 - 11:36:03

Identifiants

Collections

Citation

Christian Bertin, Claude-Pierre Jeannerod, Jingyan Jourdan-Lu, Hervé Knochel, Christophe Monat, et al.. Techniques and tools for implementing IEEE 754 floating-point arithmetic on VLIW integer processors. 4th International Workshop on Parallel and Symbolic Computation (PASCO'10), Jul 2010, Grenoble, France. ACM, pp.1-9, 2010, 〈10.1145/1837210.1837212〉. 〈ensl-00549467〉

Partager

Métriques

Consultations de la notice

152