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Techniques and tools for implementing IEEE 754 floating-point arithmetic on VLIW integer processors

Christian Bertin 1 Claude-Pierre Jeannerod 2 Jingyan Jourdan-Lu 1, 2 Hervé Knochel 1 Christophe Monat 1 Christophe Mouilleron 2 Jean-Michel Muller 2 Guillaume Revy 3
1 ST-GRENOBLE - STMicroelectronics [Grenoble]
2 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
3 ELIAUS - Electronique, Informatique, Automatique et Systèmes
Abstract : Recently, some high-performance IEEE 754 single precision floating-point software has been designed, which aims at best exploiting some features (integer arithmetic, parallelism) of the STMicroelectronics ST200 Very Long Instruction Word (VLIW) processor. We review here the techniques and software tools used or developed for this design and its implementation, and how they allowed very high instruction-level parallelism (ILP) exposure. Those key points include a hierarchical description of function evaluation algorithms, the exploitation of the standard encoding of floating-point data, the automatic generation of fast and accurate polynomial evaluation schemes, and some compiler optimizations.
Keywords : binary foating-point arithmetic correct rounding IEEE 754 polynomial evaluation instruction-level parallelism code generation C software implementation VLIW integer processor
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Conference papers
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https://hal-ens-lyon.archives-ouvertes.fr/ensl-00549467
Contributor : Claude-Pierre Jeannerod <>
Submitted on : Wednesday, December 22, 2010 - 9:11:57 AM
Last modification on : Friday, June 25, 2021 - 3:40:02 PM

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CNRS | INRIA | UNIV-PERP | LIP | ENS-LYON | UNIV-LYON1 | UDL

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Christian Bertin, Claude-Pierre Jeannerod, Jingyan Jourdan-Lu, Hervé Knochel, Christophe Monat, et al.. Techniques and tools for implementing IEEE 754 floating-point arithmetic on VLIW integer processors. 4th International Workshop on Parallel and Symbolic Computation (PASCO'10), Jul 2010, Grenoble, France. pp.1-9, ⟨10.1145/1837210.1837212⟩. ⟨ensl-00549467⟩

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