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A 128-Tap Complex FIR Filter Processing 20 Giga-Samples/s in a Single FPGA

Florent de Dinechin 1, 2 Honoré Takeugming 1, 2 Jean-Marc Tanguy 3 
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : To enable 40Gb/s data transmission over optical fibres using QPSK modulation, the first step of the receiver signal-processing pipeline is a 128-tap FIR filter that compensates the chromatic dispersion due to the medium. We present an implementation of this FIR filter in the largest Stratix-IV GX device that is able to process 20 giga-samples per second, where each sample is a complex number with 5+5 bits resolution. This FFT-based architecture processes 128 complex samples per cycles at a frequency of 156MHz. The FFT and inverse FFT pipelines use ad-hoc memory-based constant multipliers well suited to the FPGA features, while the multiplications in the Fourier domain use the FPGA embedded DSP blocks. This FPGA is thus able to perform more than 2 tera-operations per second. The precision of the intermediate signals is chosen to ensure that the error of the output signal with respect to the Matlab reference is never more than one least significant bit.
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Submitted on : Saturday, December 4, 2010 - 2:03:29 PM
Last modification on : Tuesday, October 25, 2022 - 4:24:37 PM
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Florent de Dinechin, Honoré Takeugming, Jean-Marc Tanguy. A 128-Tap Complex FIR Filter Processing 20 Giga-Samples/s in a Single FPGA. 44th Conference on signals, systems and computers, United States. ⟨ensl-00542950⟩



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