FPGA-Specific Arithmetic Optimizations of Short-Latency Adders

Hong Diep Nguyen 1 Bogdan Pasca 1 Thomas Preusser 2, *
* Auteur correspondant
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Integer addition is a pervasive operation in FPGA designs. The need for fast wide adders grows with the demand for large precisions as, for example, required for the implementation of IEEE-754 quadruple precision and eliptic-curve cryptography. The FPGA realization of fast and compact binary adders relies on hardware carry chains. These provide a natural implementation environment for the ripple-carry addition (RCA) scheme. As its latency grows linearly with the operand width, wide additions call for acceleration, which is quite reasonably achieved by addition schemes built from parallel RCA blocks. This study presents FPGA-specific arithmetic optimizations for the mapping of carry-select/increment adders targeting the hardware carry chains of modern FPGAs. Different trade-offs between latency and area are presented. The proposed architectures represent attractive alternatives to deeply pipelined RCA schemes.
Type de document :
Communication dans un congrès
2011 International Conference on Field Programmable Logic and Applications (FPL), Sep 2011, Chania, Greece. pp.232 - 237, 2011, 2011. 〈10.1109/FPL.2011.49〉
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https://hal-ens-lyon.archives-ouvertes.fr/ensl-00542389
Contributeur : Bogdan Pasca <>
Soumis le : jeudi 2 décembre 2010 - 14:37:57
Dernière modification le : vendredi 20 avril 2018 - 15:44:23
Document(s) archivé(s) le : lundi 5 novembre 2012 - 11:10:28

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Hong Diep Nguyen, Bogdan Pasca, Thomas Preusser. FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. 2011 International Conference on Field Programmable Logic and Applications (FPL), Sep 2011, Chania, Greece. pp.232 - 237, 2011, 2011. 〈10.1109/FPL.2011.49〉. 〈ensl-00542389〉

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