A. Ieee, Standard 754-1985 for Binary Floating-Point Arithmetic (also IEC 60559), 1985.

M. Arnold, T. Bailey, J. Cowles, and M. Winkel, Arithmetic co-transformations in the real and complex logarithmic number systems, IEEE Transactions on Computers, vol.47, issue.7, pp.777-786, 1998.
DOI : 10.1109/12.709377

P. Belanovi´cbelanovi´c and M. Leeser, A library of parameterized floating-point modules and their use, Field Programmable Logic and Applications, pp.657-666, 2002.

J. Beuchat and A. Tisserand, Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices, Field-Programmable Logic and Applications, 2002.
DOI : 10.1007/3-540-46117-5_54
URL : https://hal.archives-ouvertes.fr/inria-00072094

J. N. Coleman and E. I. Chester, Arithmetic on the European logarithmic microprocessor, IEEE Transactions on Computers, vol.49, issue.7, pp.702-715, 2000.
DOI : 10.1109/12.863040

F. De-dinechin and A. Tisserand, Some improvements on multipartite table methods, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, pp.128-135, 2001.
DOI : 10.1109/ARITH.2001.930112
URL : https://hal.archives-ouvertes.fr/inria-00072577

M. Delorimier and A. Dehon, Floating-point sparse matrix-vector multiply for FPGAs, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, pp.75-85, 2005.
DOI : 10.1145/1046192.1046203

J. Detrey and F. De-dinechin, A VHDL library of LNS operators, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003, 2003.
DOI : 10.1109/ACSSC.2003.1292376

J. Detrey and F. De-dinechin, Second Order Function Approximation Using a Single Multiplication on FPGAs, 14th Intl Conference on Field-Programmable Logic and Applications (LNCS 3203), pp.221-230, 2004.
DOI : 10.1007/978-3-540-30117-2_24

J. Dido, N. Geraudie, L. Loiseau, O. Payeur, Y. Savaria et al., A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays , FPGA '02, pp.50-55, 2002.
DOI : 10.1145/503048.503056

C. Doss and R. Riley, FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2004.
DOI : 10.1109/FCCM.2004.38

Y. Dou, S. Vassiliadis, G. K. Kuzmanov, and G. N. Gaydadjiev, 64-bit floating-point FPGA matrix multiplication, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, 2005.
DOI : 10.1145/1046192.1046204

M. D. Ercegovac and T. Lang, Division and Square Root: Digit-Recurrence Algorithms and Implementations, 1994.

M. D. Ercegovac and T. Lang, Digital Arithmetic, 2003.
URL : https://hal.archives-ouvertes.fr/ensl-00542215

M. J. Flynn and S. F. Oberman, Advanced Computer Arithmetic Design, 2001.

A. A. Gaffar, W. Luk, P. Y. Cheung, N. Shirazi, and J. Hwang, Automating Customisation of Floating-Point Designs, Field Programmable Logic and Applications, pp.523-533, 2002.
DOI : 10.1007/3-540-46117-5_55

D. Goldberg, What every computer scientist should know about floating-point arithmetic, ACM Computing Surveys, vol.23, issue.1, pp.5-47, 1991.
DOI : 10.1145/103162.103163
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1.7712

M. Haselman, M. Beauchamp, K. Underwood, and K. S. Hemmert, A Comparison of Floating Point and Logarithmic Number Systems for FPGAs, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), 2005.
DOI : 10.1109/FCCM.2005.6

B. Lee and N. Burgess, Parameterisable floating-point operators on FPGAs, 36th Asilomar Conference on Signals, Systems, and Computers, pp.1064-1068, 2002.

B. Lee and N. Burgess, A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA, Field-Programmable Logic and Applications, 2003.
DOI : 10.1007/978-3-540-45234-8_78

D. M. Lewis, An architecture for addition and subtraction of long word length numbers in the logarithmic number system, IEEE Transactions on Computers, vol.39, issue.11, 1990.
DOI : 10.1109/12.61042

G. Lienhart, A. Kugel, and R. Männer, Using floating-point arithmetic on FPGAs to accelerate scientific N-Body simulations, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2002.
DOI : 10.1109/FPGA.2002.1106673

R. Matou?ek, M. Tichý, Z. Pohl, J. Kadlec, C. Softley et al., Logarithmic Number System and Floating-Point Arithmetics on FPGA, Field-Programmable Logic and Applications, pp.627-636, 2002.
DOI : 10.1007/3-540-46117-5_65

F. Ortiz, J. Humphrey, J. Durbano, and D. Prather, A Study on the Design of Floating-Point Functions in FPGAs, Field Programmable Logic and Applications, pp.1131-1135, 2003.
DOI : 10.1007/978-3-540-45234-8_137

V. Paliouras and T. Stouraitis, A novel algorithm for accurate logarithmic number system subtraction, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96, pp.268-271, 1996.
DOI : 10.1109/ISCAS.1996.542021

E. Roesler and B. Nelson, Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture, Field Programmable Logic and Applications, pp.637-646, 2002.
DOI : 10.1007/3-540-46117-5_66

F. J. Taylor, R. Gill, J. Joseph, and J. Radke, A 20 bit logarithmic number system processor, IEEE Transactions on Computers, vol.37, issue.2, 1988.
DOI : 10.1109/12.2148