A. Ieee, Standard 754-1985 for Binary Floating-Point Arithmetic (also IEC 60559, 1985.

I. Iec, I. Standard, and I. Iec, (E) Programming languages ? C, p.1999, 1999.

G. Paul and M. W. Wilson, Should the Elementary Function Library Be Incorporated Into Computer Instruction Sets?, ACM Transactions on Mathematical Software, vol.2, issue.2, pp.132-142, 1976.
DOI : 10.1145/355681.355684

M. Ercegovac, Radix-16 Evaluation of Certain Elementary Functions, IEEE Transactions on Computers, vol.22, issue.6, pp.561-566, 1973.
DOI : 10.1109/TC.1973.5009107

C. Wrathall and T. C. Chen, Convergence guarantee and improvements for a fast hardware exponential and logarithm evaluation scheme, 1978 IEEE 4th Symposium onomputer Arithmetic (ARITH), pp.175-182, 1978.
DOI : 10.1109/ARITH.1978.6155762

P. Farmwald, High bandwidth evaluation of elementary functions, 1981 IEEE 5th Symposium on Computer Arithmetic (ARITH), pp.139-142, 1981.
DOI : 10.1109/ARITH.1981.6159271

M. Cosnard, A. Guyot, B. Hochet, J. M. Muller, H. Ouaouicha et al., The FELIN arithmetic coprocessor chip, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH), pp.107-112, 1987.
DOI : 10.1109/ARITH.1987.6158691

URL : https://hal.archives-ouvertes.fr/hal-00014979

W. F. Wong and E. Goto, Fast hardware-based algorithms for elementary function computations using rectangular multipliers, IEEE Transactions on Computers, vol.43, issue.3, pp.278-294, 1994.
DOI : 10.1109/12.272429

P. T. Tang, Table-driven implementation of the exponential function in IEEE floating-point arithmetic, ACM Transactions on Mathematical Software, vol.15, issue.2, pp.144-157, 1989.
DOI : 10.1145/63522.214389

C. S. Anderson, S. Story, and N. Astafiev, Accurate math functions on the Intel IA-32 architecture: A performance-driven design, 7th Conference on Real Numbers and Computers, pp.93-105, 2006.

H. Hassler and N. Takagi, Function evaluation by table look-up and addition, Proceedings of the 12th Symposium on Computer Arithmetic, pp.10-16, 1995.
DOI : 10.1109/ARITH.1995.465382

J. Stine and M. Schulte, The symmetric table addition method for accurate function approximation, The Journal of VLSI Signal Processing, vol.21, issue.2, pp.167-177, 1999.
DOI : 10.1023/A:1008004523235

D. Lee, A. Gaffar, O. Mencer, and W. Luk, Optimizing Hardware Function Evaluation, IEEE Transactions on Computers, vol.54, issue.12, pp.1520-1531, 2005.
DOI : 10.1109/TC.2005.201

J. Detrey and F. De-dinechin, Table-based polynomials for fast hardware function evaluation, " in Application-specific Systems, Architectures and Processors, pp.328-333, 2005.

K. Underwood, FPGAs vs. CPUs, Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays , FPGA '04, 2004.
DOI : 10.1145/968280.968305

D. Strenski, J. Simkins, R. Walke, and R. Wittig, Revaluating FPGAs for 64-bit floating-point calculations, HPC wire, 2008.

G. Lienhart, A. Kugel, and R. Männer, Using floating-point arithmetic on FPGAs to accelerate scientific N-Body simulations, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2002.
DOI : 10.1109/FPGA.2002.1106673

M. Delorimier and A. Dehon, Floating-point sparse matrix-vector multiply for FPGAs, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, pp.75-85, 2005.
DOI : 10.1145/1046192.1046203

Y. Dou, S. Vassiliadis, G. K. Kuzmanov, and G. N. Gaydadjiev, 64-bit floating-point FPGA matrix multiplication, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, pp.86-95, 2005.
DOI : 10.1145/1046192.1046204

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

F. De-dinechin, J. Detrey, I. Trestian, O. Cret¸, R. Cret¸ et al., When FPGAs are better at floating-point than microprocessors, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays , FPGA '08, 2007.
DOI : 10.1145/1344671.1344717

URL : https://hal.archives-ouvertes.fr/ensl-00174627

J. Detrey and F. De-dinechin, Parameterized floating-point logarithm and exponential functions for FPGAs, Microprocessors and Microsystems, Special Issue on FPGA-based Reconfigurable Computing, pp.537-545, 2007.
DOI : 10.1016/j.micpro.2006.02.008

URL : https://hal.archives-ouvertes.fr/ensl-00542213

J. Muller, Elementary Functions, Algorithms and Implementation, 2006.
URL : https://hal.archives-ouvertes.fr/ensl-00000008

J. Detrey, F. De-dinechin, and X. Pujol, Return of the hardware floating-point elementary function, 18th IEEE Symposium on Computer Arithmetic (ARITH '07), pp.161-168, 2007.
DOI : 10.1109/ARITH.2007.29

URL : https://hal.archives-ouvertes.fr/ensl-00117386

F. De-dinechin and B. Pasca, Large multipliers with fewer DSP blocks, 2009 International Conference on Field Programmable Logic and Applications, 2009.
DOI : 10.1109/FPL.2009.5272296

K. Chapman, Fast integer multipliers fit in FPGAs (EDN 1993 design idea winner), " EDN magazine, 1994.

F. De-dinechin, C. Klein, and B. Pasca, Generating highperformance custom floating-point pipelines, Field Programmable Logic and Applications. IEEE, 2009.
URL : https://hal.archives-ouvertes.fr/ensl-00379154

M. Cornea, J. Harrison, and P. T. Tang, Scientific Computing on Itanium R -based Systems, 2002.

N. Brisebarre and S. Chevillard, Efficient polynomial L-approximations, 18th IEEE Symposium on Computer Arithmetic (ARITH '07), pp.169-176, 2007.
DOI : 10.1109/ARITH.2007.17

URL : https://hal.archives-ouvertes.fr/inria-00119513

J. Detrey and F. De-dinechin, Floating-point trigonometric functions for FPGAs, " in Field-Programmable Logic and Applications, IEEE, pp.29-34, 2007.