Skip to Main content Skip to Navigation
Preprints, Working Papers, ...

A flexible floating-point logarithm for reconfigurable computers

Florent de Dinechin 1, 2 
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : The advent of reconfigurable co-processors based on field-programmable gate arrays has renewed interest in hardware architectures for elementary functions. This article studies operators for the logarithm function in the context of this target technology. An old algorithm is generalized, fine-tuned and implemented as an architecture generator, exposing a wide range of trade-offs between resources (memory, logic and multipliers) and performance (frequency and pipeline depth). A single pipelined operator computes five times more double-precision floating-point logarithms per second than a high-end processor core, while consuming only a few percents of the resources of a high-end FPGA. This generator is available under the LGPL as part of the FloPoCo project.
Document type :
Preprints, Working Papers, ...
Complete list of metadata

Cited literature [29 references]  Display  Hide  Download
Contributor : Florent de Dinechin Connect in order to contact the contributor
Submitted on : Tuesday, July 27, 2010 - 12:06:27 PM
Last modification on : Friday, February 4, 2022 - 3:19:20 AM
Long-term archiving on: : Tuesday, October 23, 2012 - 11:30:26 AM


Files produced by the author(s)


  • HAL Id : ensl-00506122, version 1



Florent de Dinechin. A flexible floating-point logarithm for reconfigurable computers. 2010. ⟨ensl-00506122⟩



Record views


Files downloads