Multipliers for Floating-Point Double Precision and Beyond on FPGAs - Archive ouverte HAL Access content directly
Conference Papers Year : 2010

Multipliers for Floating-Point Double Precision and Beyond on FPGAs

(1) , (2, 3) , (2, 3) , (1)
1
2
3

Abstract

The implementation of high-precision floating-point applications on reconfigurable hardware requires a variety of large multipliers: Standard multipliers are the core of floating-point multipliers; Truncated multipliers, trading resources for a well-controlled accuracy degradation, are useful building blocks in situations where a full multiplier is not needed. This work studies the automated generation of such multipliers using the embedded multipliers and adders present in DSP blocks of current FPGAs. The optimization of such multipliers is expressed as a tiling problem where a tile represents a hardware multiplier and super-tiles are the wiring of several hardware multipliers making efficient use of the DSP internal resources. This tiling technique is shown to adapt to full or truncated multipliers. It addresses arbitrary precisions including single, double but also in the quadruple precision introduced by the IEEE-754-2008 standard and currently unsupported by processor hardware. An open-source implementation is provided in the FloPoCo project.
Fichier principal
Vignette du fichier
dpbt.pdf (272.52 Ko) Télécharger le fichier
Origin : Files produced by the author(s)
Loading...

Dates and versions

ensl-00475781 , version 1 (22-04-2010)
ensl-00475781 , version 2 (01-11-2010)

Identifiers

  • HAL Id : ensl-00475781 , version 2

Cite

Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, Radu Tudoran. Multipliers for Floating-Point Double Precision and Beyond on FPGAs. Highly Efficient Accelerators and Reconfigurable Technologies, Jun 2010, Tsukuba, Japan. ⟨ensl-00475781v2⟩
233 View
776 Download

Share

Gmail Facebook Twitter LinkedIn More