Pipelined FPGA Adders

Florent De Dinechin 1, 2 Hong Diep Nguyen 1, 2 Bogdan Pasca 1, 2
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Integer addition is a universal building block, and applications such as quad-precision floating-point or elliptic curve cryptography now demand precisions well beyond 64 bits. This study explores the trade-offs between size, latency and frequency for pipelined large-precision adders on FPGA. It compares three pipelined adder architectures: the classical pipelined ripple-carry adder, a variation that reduces register count, and an FPGA-specific implementation of the carry-select adder capable of providing lower latency additions at a comparable price. For each of these architectures, resource estimation models are defined, and used in an adder generator that selects the best architecture considering the target FPGA, the target operating frequency, and the addition bit width.
keyword : Adder Pipeline FPGA
Type de document :
Communication dans un congrès
International Conference on Field Programmable Logic and Applications, Aug 2010, Milano, Italy. IEEE, pp.422-427, 2010, 〈10.1109/FPL.2010.87〉
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Contributeur : Bogdan Pasca <>
Soumis le : lundi 1 novembre 2010 - 12:02:27
Dernière modification le : vendredi 20 avril 2018 - 15:44:24
Document(s) archivé(s) le : vendredi 2 décembre 2016 - 04:41:17

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Florent De Dinechin, Hong Diep Nguyen, Bogdan Pasca. Pipelined FPGA Adders. International Conference on Field Programmable Logic and Applications, Aug 2010, Milano, Italy. IEEE, pp.422-427, 2010, 〈10.1109/FPL.2010.87〉. 〈ensl-00475780v2〉

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