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Conference Papers Year : 2010

Automatic generation of polynomial-based hardware architectures for function evaluation

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Abstract

Many applications require the evaluation of some function through polynomial approximation. This article details an architecture generator for this class of problems that improves upon the literature in two aspects. Firstly, it benefits from recent advances related to constrained-coefficient polynomial approximation. Secondly, it refines the error analysis of polynomial evaluation to reduce the size of the multipliers used. As a result, architectures for evaluating arbitrary functions with precisions up to 64 bits, making efficient use of the resources of recent FPGAs, can be obtained in seconds. An open-source implementation is provided in the FloPoCo project.
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Dates and versions

ensl-00470506 , version 1 (06-04-2010)

Identifiers

  • HAL Id : ensl-00470506 , version 1

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Florent de Dinechin, Mioara Joldes, Bogdan Pasca. Automatic generation of polynomial-based hardware architectures for function evaluation. Application-specific Systems, Architectures and Processors, Jul 2010, Rennes, France. ⟨ensl-00470506⟩
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