Design and Implementation of a Radix-4 Complex Division Unit with Prescaling

Pouya Dormiani; Milos Ercegovac; Jean-Michel Muller

Design and Implementation of a Radix-4 Complex Division Unit with Prescaling

Pouya Dormiani ¹ Milos Ercegovac ¹ Jean-Michel Muller ^{2, 3}

1 Digital Arithmetic and Reconfigurable Architecture Laboratory

2 ARENAIRE - Computer arithmetic

Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme

3 LIP - Laboratoire de l'Informatique du Parallélisme

Abstract : We present a design and implementation of a radix-4 complex division unit with prescaling of the operands. Specifically, we extend the treatment of the residual bound and errors due to the use of truncated redundant representation. The requirements for prescaling tables are simplified and a detailed specification of the table design is given. All principal components used in the design are described and the proposed optimizations are explained. The target platform for implementation was an Altera Stratix II FPGA [15] for which we report timing and area requirements. For a precision of 36 bits, the implementation uses 1093 ALUTs, achieving a latency of 97ns. The maximum clock frequency is 268.53 MHz.

Keywords : computer arithmetic complex arithmetic division digit-recurrence algorithms prescaling

Document type :

Conference papers

Domain :

Computer Science [cs] / Other [cs.OH]

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https://hal-ens-lyon.archives-ouvertes.fr/ensl-00379147
Contributor : Jean-Michel Muller <>
Submitted on : Wednesday, January 13, 2010 - 3:41:05 PM
Last modification on : Wednesday, August 7, 2019 - 12:14:40 PM
Long-term archiving on : Wednesday, November 30, 2016 - 10:37:29 AM

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Design and Implementation of a Radix-4 Complex Division Unit with Prescaling

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