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Design and Implementation of a Radix-4 Complex Division Unit with Prescaling

Abstract : We present a design and implementation of a radix-4 complex division unit with prescaling of the operands. Specifically, we extend the treatment of the residual bound and errors due to the use of truncated redundant representation. The requirements for prescaling tables are simplified and a detailed specification of the table design is given. All principal components used in the design are described and the proposed optimizations are explained. The target platform for implementation was an Altera Stratix II FPGA [15] for which we report timing and area requirements. For a precision of 36 bits, the implementation uses 1093 ALUTs, achieving a latency of 97ns. The maximum clock frequency is 268.53 MHz.
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Contributor : Jean-Michel Muller <>
Submitted on : Monday, April 27, 2009 - 5:00:54 PM
Last modification on : Friday, September 10, 2021 - 2:34:03 PM
Long-term archiving on: : Monday, October 15, 2012 - 9:25:24 AM


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  • HAL Id : ensl-00379147, version 1



Pouya Dormiani, Milos Ercegovac, Jean-Michel Muller. Design and Implementation of a Radix-4 Complex Division Unit with Prescaling. 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'09), Jul 2009, Boston, United States. ⟨ensl-00379147v1⟩



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