Large multipliers with less DSP blocks

Florent De Dinechin 1 Bogdan Pasca 1
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Recent computing-oriented FPGAs feature DSP blocks including small embedded multipliers. A large integer multiplier, for instance for a double-precision floating-point multiplier, consumes many of these DSP blocks. This article studies three non-standard implementation techniques of large multipliers: the Karatsuba-Ofman algorithm, non-standard multiplier tiling, and specialized squarers. They allow for large multipliers working at the peak frequency of the DSP blocks while reducing the DSP block usage. Their overhead in term of logic resources, if any, is much lower than that of emulating embedded multipliers. Their latency overhead, if any, is very small. Complete algorithmic descriptions are provided, carefully mapped on recent Xilinx and Altera devices, and validated by synthesis results.
Type de document :
Communication dans un congrès
Field Programmable Logic and Applications, Aug 2009, Czech Republic. IEEE, 2009
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https://hal-ens-lyon.archives-ouvertes.fr/ensl-00356421
Contributeur : Florent De Dinechin <>
Soumis le : mardi 27 janvier 2009 - 14:43:37
Dernière modification le : vendredi 20 avril 2018 - 15:44:23
Document(s) archivé(s) le : vendredi 12 octobre 2012 - 10:20:15

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  • HAL Id : ensl-00356421, version 1

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Florent De Dinechin, Bogdan Pasca. Large multipliers with less DSP blocks. Field Programmable Logic and Applications, Aug 2009, Czech Republic. IEEE, 2009. 〈ensl-00356421〉

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