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Generating high-performance arithmetic operators for FPGAs

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Abstract

This article addresses the development of complex, heavily parameterized and flexible operators to be used in FPGA-based floating-point accelerators. Languages such as VHDL or Verilog are not ideally suited for this task. The main problem is the automation of problems such as parameter-directed or target-directed architectural optimization, pipeline optimization, and generation of relevant test benches. This article introduces FloPoCo, an open object-oriented software framework designed to address these issues. Written in C++, it inputs operator specifications, a target FPGA and and an objective frequency, and outputs synthesisable VHDL fine-tuned for this FPGA at this frequency. Its design choices are discussed and validated on various operators.
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Dates and versions

ensl-00321209 , version 1 (12-09-2008)

Identifiers

  • HAL Id : ensl-00321209 , version 1

Cite

Florent de Dinechin, Cristian Klein, Bogdan Pasca. Generating high-performance arithmetic operators for FPGAs. 2008. ⟨ensl-00321209⟩
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