P. Belanovi´cbelanovi´c and M. Leeser, A library of parameterized floating-point modules and their use, Field Programmable Logic and Applications, pp.657-666, 2002.

M. R. Bodnar, J. R. Humphrey, P. F. Curt, J. P. Durbano, and D. W. Prather, Floating-Point Accumulation Circuit for Matrix Applications, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp.303-304, 2006.
DOI : 10.1109/FCCM.2006.41

O. Cret¸, F. Cret¸, I. De-dinechin, R. Trestian, L. Tudoran et al., FPGA-Based Acceleration of the Computations Involved in Transcranial Magnetic Stimulation, 2008 4th Southern Conference on Programmable Logic, pp.43-48, 2008.
DOI : 10.1109/SPL.2008.4547730

M. Delorimier and A. Dehon, Floating-point sparse matrix-vector multiply for FPGAs, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, pp.75-85, 2005.
DOI : 10.1145/1046192.1046203

Y. Dou, S. Vassiliadis, G. K. Kuzmanov, and G. N. Gaydadjiev, 64-bit floating-point FPGA matrix multiplication, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, pp.86-95, 2005.
DOI : 10.1145/1046192.1046204

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

H. A. Fahmy and M. J. Flynn, The case for a redundant format in floating point arithmetic, 16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings., pp.95-102, 2003.
DOI : 10.1109/ARITH.2003.1207665

C. He, G. Qin, M. Lu, and W. Zhao, Group-alignment based accurate floating-point summation on FPGAs, ERSA, pp.136-142, 2006.

U. W. Kulisch, Advanced Arithmetic for the Digital Computer, Design of Arithmetic Units, Electronic Notes in Theoretical Computer Science, vol.24, 2002.
DOI : 10.1016/S1571-0661(05)80622-X

B. Lee and N. Burgess, Parameterisable floating-point operators on FPGAs, 36th Asilomar Conference on Signals, Systems, and Computers, pp.1064-1068, 2002.
DOI : 10.1109/acssc.2002.1196947

Y. Li and W. Chu, Implementation of single precision floating point square root on FPGAs, IEEE Symposium on FPGAs for Custom Computing Machines, pp.56-65, 1997.

G. Lienhart, A. Kugel, and R. Männer, Using floatingpoint arithmetic on FPGAs to accelerate scientific Nbody simulations, FPGAs for Custom Computing Machines. IEEE, 2002.
DOI : 10.1109/fpga.2002.1106673

W. Ligon, S. Mcmillan, G. Monn, K. Schoonover, F. Stivers et al., A re-evaluation of the practicality of floating-point operations on FPGAs, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251), 1998.
DOI : 10.1109/FPGA.1998.707898

J. Liu, M. Chang, and C. Cheng, An iterative division algorithm for FPGAs, Proceedings of the internation symposium on Field programmable gate arrays , FPGA'06, pp.83-89, 2006.
DOI : 10.1145/1117201.1117213

Z. Luo and M. Martonosi, Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques, IEEE Transactions on Computers, vol.49, issue.3, pp.208-218, 2000.
DOI : 10.1109/12.841125

E. Roesler and B. Nelson, Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture, Field Programmable Logic and Applications, pp.637-646, 2002.
DOI : 10.1007/3-540-46117-5_66

N. Shirazi, A. Walters, and P. Athanas, Quantitative analysis of floating point arithmetic on FPGA based custom computing machine [17] L. Zhuo and V. Prasanna. Scalable and modular algorithms for floating-point matrix multiplication on FP- GAs, FPGAs for Custom Computing Machines Reconfigurable Architecture Workshop, Intl. Parallel and Distributed Processing Symposium, pp.155-162, 1995.

L. Zhuo and V. K. Prasanna, High performance linear algebra operations on reconfigurable systems, ACM/IEEE conference on Supercomputing. IEEE, 2005.