Architectural modifications to improve floating-point unit efficiency in FP- GAs, Field Programmable Logic and Applications, pp.1-6, 2005. ,
Embedded floating-point units in FPGAs, Proceedings of the internation symposium on Field programmable gate arrays , FPGA'06, pp.12-20, 2006. ,
DOI : 10.1145/1117201.1117204
Correctly rounded multiplication by arbitrary precision constants, Proc. 17th IEEE Symposium on Computer Arithmetic (ARITH-17, 2005. ,
URL : https://hal.archives-ouvertes.fr/ensl-00000010
Fast integer multipliers fit in FP- GAs (EDN 1993 design idea winner) EDN magazine, 1994. ,
Assisted verification of elementary functions using Gappa, Proceedings of the 2006 ACM symposium on Applied computing , SAC '06, pp.1318-1322, 2006. ,
DOI : 10.1145/1141277.1141584
Constant multipliers for FPGAs, Parallel and Distributed Processing Techniques and Applications, pp.167-173, 2000. ,
URL : https://hal.archives-ouvertes.fr/ensl-00269219
Optimistic parallelization of floating-point accumulation, 18th Symposium on Computer Arithmetic, pp.205-213, 2007. ,
Floating-point sparse matrix-vector multiply for FPGAs, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, pp.75-85, 2005. ,
DOI : 10.1145/1046192.1046203
Table-based polynomials for fast hardware function evaluation [10] J. Detrey and F. de Dinechin. Floating-point trigonometric functions for FPGAs, Application-specific Systems, Architectures and Processors Intl Conference on Field-Programmable Logic and Applications, pp.328-333, 2005. ,
DOI : 10.1109/asap.2005.61
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.164.327
Parameterized floating-point logarithm and exponential functions for FPGAs, Microprocessors and Microsystems, 2007. ,
DOI : 10.1016/j.micpro.2006.02.008
URL : https://hal.archives-ouvertes.fr/ensl-00542213
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic, The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol.23, issue.1, 2007. ,
DOI : 10.1007/s11265-007-0048-7
URL : https://hal.archives-ouvertes.fr/ensl-00542212
Return of the hardware floating-point elementary function, 18th IEEE Symposium on Computer Arithmetic (ARITH '07), pp.161-168, 2007. ,
DOI : 10.1109/ARITH.2007.29
URL : https://hal.archives-ouvertes.fr/ensl-00117386
Multiplication by a Constant is Sublinear, 18th IEEE Symposium on Computer Arithmetic (ARITH '07), 2007. ,
DOI : 10.1109/ARITH.2007.24
URL : https://hal.archives-ouvertes.fr/lirmm-00158322
FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp.229-238, 2004. ,
DOI : 10.1109/FCCM.2004.38
64-bit floating-point FPGA matrix multiplication, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, pp.86-95, 2005. ,
DOI : 10.1145/1046192.1046204
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.108.9463
Advanced Computer Arithmetic Design, 2001. ,
What every computer scientist should know about floating-point arithmetic, ACM Computing Surveys, vol.23, issue.1, pp.5-47, 1991. ,
DOI : 10.1145/103162.103163
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1.7712
Accuracy and stability of numerical algorithms, SIAM, 1996. ,
DOI : 10.1137/1.9780898718027
Seminumerical Algorithms, The Art of Computer Programming, 1997. ,
Circuitry for generating scalar products and sums of floating point numbers with maximum accuracy, 1986. ,
Advanced Arithmetic for the Digital Computer, Design of Arithmetic Units, Electronic Notes in Theoretical Computer Science, vol.24, 2002. ,
DOI : 10.1016/S1571-0661(05)80622-X
Exploiting the Performance of 32 bit Floating Point Arithmetic in Obtaining 64 bit Accuracy (Revisiting Iterative Refinement for Linear Systems), ACM/IEEE SC 2006 Conference (SC'06), 2006. ,
DOI : 10.1109/SC.2006.30
Parameterisable floating-point operators on FPGAs, 36th Asilomar Conference on Signals, Systems, and Computers, pp.1064-1068, 2002. ,
Optimizing Hardware Function Evaluation, IEEE Transactions on Computers, vol.54, issue.12, pp.1520-1531, 2005. ,
DOI : 10.1109/TC.2005.201
Multiplication by an integer constant, 1999. ,
Implementation of single precision floating point square root on FPGAs, IEEE Symposium on FPGAs for Custom Computing Machines, pp.56-65, 1997. ,
Using floating-point arithmetic on FPGAs to accelerate scientific N-Body simulations, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2002. ,
DOI : 10.1109/FPGA.2002.1106673
A re-evaluation of the practicality of floating-point operations on FPGAs, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251), 1998. ,
DOI : 10.1109/FPGA.1998.707898
An iterative division algorithm for FPGAs, Proceedings of the internation symposium on Field programmable gate arrays , FPGA'06, pp.83-89 ,
DOI : 10.1145/1117201.1117213
IA-64 and Elementary Functions: Speed and Precision. Hewlett-Packard Professional Books, 2000. ,
Feasibility of floating-point arithmetic in FPGA based artificial neural networks, In CAINE, pp.8-13, 2002. ,
Design issues in division and other floating-point operations, IEEE Transactions on Computers, vol.46, issue.2, pp.154-161, 1997. ,
DOI : 10.1109/12.565590
Accurate Sum and Dot Product, SIAM Journal on Scientific Computing, vol.26, issue.6, pp.1955-1988, 2005. ,
DOI : 10.1137/030601818
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.2.1547
A study on the design of floatingpoint functions in FPGAs, Field Programmable Logic and Applications, pp.1131-1135, 2003. ,
Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture, Field Programmable Logic and Applications, pp.637-646, 2002. ,
DOI : 10.1007/3-540-46117-5_66
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines, pp.155-162, 1995. ,
DOI : 10.1109/FPGA.1995.477421
A hardware algorithm for computing reciprocal square root, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, pp.94-100, 2001. ,
DOI : 10.1109/ARITH.2001.930108
A VLSI algorithm for computing the euclidean norm of a 3D vector, IEEE Transactions on Computers, vol.49, issue.10, pp.1074-1082, 2000. ,
FPGAbased computation of the inductance of coils used for the magnetic stimulation of the nervous system, 2007. ,
URL : https://hal.archives-ouvertes.fr/ensl-00169909
Scalable and modular algorithms for floating-point matrix multiplication on FPGAs, Reconfigurable Architecture Workshop, Intl. Parallel and Distributed Processing Symposium, 2004. ,