Abstract : This paper aims at surveying multipliers based on Horner's rule for finite field arithmetic. We present a generic architecture based on five processing elements and introduce a classification of several algorithms based on our model. We provide the readers with a detailed description of each scheme which should allow them to write a VHDL description or a VHDL code generator.
https://hal-ens-lyon.archives-ouvertes.fr/ensl-00148210
Contributeur : Jean-Michel Muller
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Soumis le : mardi 22 mai 2007 - 09:37:33
Dernière modification le : mardi 24 avril 2018 - 13:52:29
Document(s) archivé(s) le : jeudi 8 avril 2010 - 17:22:10
Jean-Michel Muller, Jean-Luc Beuchat, Takanori Miyoshi, Eiji Okamoto. Horner's Rule-Based Multiplication over Fp and Fp^n: A Survey. International Journal of Electronics, Taylor & Francis, 2008, 95 (7), pp.669-685. 〈ensl-00148210〉
