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Automatic Generation of Modular Multipliers for FPGA Applications

Abstract : Since redundant number systems allow constant time addition, they are often at the heart of modular multipliers designed for public key cryptography (PKC) applications. Indeed, PKC involves large operands (160 to 1024 bits) and several researchers proposed carry-save or borrow-save algorithms. However, these number systems do not take advantage of the dedicated carry logic available in modern Field Programmable Gate Arrays (FPGAs). To overcome this problem, we suggest to perform modular multiplication in a high-radix carry-save number system, where a sum bit of the carry-save representation is replaced by a sum word. Two digits are then added by means of a small Carry-Ripple Adder (CRA). Furthermore, we propose an algorithm which selects the best high-radix carry-save representation for a given modulus, and generates a synthesizable VHDL description of the operator.
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Contributor : Jean-Michel Muller Connect in order to contact the contributor
Submitted on : Monday, November 24, 2008 - 10:48:01 AM
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Jean-Michel Muller, Jean-Luc Beuchat. Automatic Generation of Modular Multipliers for FPGA Applications. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2008, 57 (12), pp.1600-1613. ⟨10.1109/TC.2008.102⟩. ⟨ensl-00122716v3⟩



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