Table-based division by small integer constants

Florent de Dinechin (1, 2) , Laurent-Stéphane Didier (3)

1 LIP - Laboratoire de l'Informatique du Parallélisme
2 ARIC - Arithmetic and Computing
3 PEQUAN - Performance et Qualité des Algorithmes Numériques

Computing cores to be implemented on FPGAs may involve divisions by small integer constants in fixed or floating point. This article presents a family of architectures addressing this need. They are derived from a simple recurrence whose body can be implemented very efficiently as a look-up table that matches the hardware resources of the target FPGA. For instance, division of a 32-bit integer by the constant 3 may be implemented by a combinatorial circuit of 48 LUT6 on a Virtex-5. Other options are studied, including iterative implementations, and architectures based on embedded memory blocks. This technique also computes the remainder. An efficient implementation of the correctly rounded division of a floating-point constant by such a small integer is also presented.

Domaines: Arithmétique des ordinateurs

Florent de Dinechin, Laurent-Stéphane Didier. Table-based division by small integer constants. 8th International Symposium on Applied Reconfigurable Computing (ARC), Mar 2012, Hong Kong, Hong Kong SAR China. pp.53-63, ⟨10.1007/978-3-642-28365-9_5⟩. ⟨ensl-00642145⟩