| Identifiant de l'article : |
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ensl-00122716, version 3 |
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| Domaine : |
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Informatique/Autre
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| Titre : |
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Automatic Generation of Modular Multipliers for FPGA Applications |
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| Auteur(s) : |
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Jean-Michel Muller1, Jean-Luc Beuchat2 |
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| Laboratoire : |
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| 1 : |
LIP - Laboratoire de l'Informatique du Parallélisme |
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Laboratory of Cryptography and Informantion Security |
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| Équipe de recherche : |
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[ARENAIRE - Arithmétique des ordinateurs] |
| Résumé : |
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Since redundant number systems allow constant time addition, they are often at the heart of modular multipliers designed for public key cryptography (PKC) applications. Indeed, PKC involves large operands (160 to 1024 bits) and several researchers proposed carry-save or borrow-save algorithms. However, these number systems do not take advantage of the dedicated carry logic available in modern Field Programmable Gate Arrays (FPGAs). To overcome this problem, we suggest to perform modular multiplication in a high-radix carry-save number system, where a sum bit of the carry-save representation is replaced by a sum word. Two digits are then added by means of a small Carry-Ripple Adder (CRA). Furthermore, we propose an algorithm which selects the best high-radix carry-save representation for a given modulus, and generates a synthesizable VHDL description of the operator. |
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Langue du texte
intégral : |
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Anglais |
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| Mots-clés : |
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modular multiplication – computer arithmetic – FPGA |
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| Commentaire : |
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Version publiée dans IEEE Transactions on Computers |
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| Référence interne : |
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LIP Research Report No 2007–1 |
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